1. Field of the Invention
The present invention relates to a constant current source circuit, and more particularly to a constant current source circuit which includes field-effect transistors (hereinafter referred to as FETs) formed on a compound semiconductor substrate such as a semiinsulating gallium arsenide (GaAs) substrate for supplying a constant current to integrated circuits.
2. Description of Related Art
Conventional constant current source circuits of this type may include a circuit, as shown in FIG. 1, in which the source region (S) and gate (G) of an FET Q are connected to the same power voltage supply line 301 to fix its gate-source voltage (hereinafter referred to as V.sub.GS) to zero and to thereby use the drain region (D) as a current source terminal 302. Another circuit is shown in FIG. 2, in which a resistor element R is inserted between the source region (S) of the FET Q and the power voltage supply line 301 and either an internally generated constant voltage or an externally supplied constant voltage is applied to a gate terminal 303 to thereby use the drain region (D) of the FET Q as the current source terminal 302. Either circuit causes the FET to operate at the saturation state, thereby supplying a constant current by utilizing the constant current characteristic inherent in the FET Q.
The above-mentioned conventional constant current source circuits exhibit an excellent constant current characteristic as far as the threshold voltage (hereinafter referred to as V.sub.T) of the FET is constant, that is, V.sub.T keep its design value. However, the V.sub.T of FETs is inevitably deviated to some extent from the design value by manufacturing conditions, etc. and the current flowing source-drain of the FET at the saturation state is proportional to the square of the V.sub.T. Therefore, large deviations in current supplied to integrated circuits through the output node of the constant current source circuit are caused from the design value of the current, thereby resulting in reduced noise margins or increased deviations of output levels from their design values for the logic circuits and output circuits utilizing the supplied current.